A bus system, such as a controlled area network (CAN) or a local interconnect network (LIN) bus system, typically connects several electronic modules or devices via a network cable, such as a single twisted-pair cable. The devices connected to a CAN bus system are typically actuators, sensors or control devices, also known as nodes. The CAN bus system enables these nodes to communicate without the use of a host computer by transmitting and receiving messages. A message comprises primarily an identifier (ID) which indicates the priority of the message and up to eight bytes of data. Messages are transmitted serially onto the bus.
Each node typically comprises a host processor, a CAN controller and a transceiver. The host processor determines which messages to transmit and deciphers messages that are received. Sensors, actuators and control devices may be connected to the host processor. The CAN controller stores transmitted messages received from the host processor and stores received bits serially received from the bus until an entire message is available. The received message is then retrieved by the host processor usually after the CAN controller has triggered an interrupt. Each node also comprises a transceiver for receiving and transmitting messages between the CAN controller and the system bus. The transceiver adapts signal levels from the bus to levels that the CAN controller expects and further comprises protective circuitry for protecting the CAN controller. The transceiver also converts the transmit-bit signal received from the CAN controller into a signal that is sent onto the bus.
On the CAN bus, a dominant (logic 0) value on the bus is created by driving the CAN bus line with a low impedance driver. A recessive (logic 1) level is transmitted by releasing the bus line which allows the CAN node pullup resistor to pull the CAN bus line to logic 1 level. This occurs when all CAN nodes release the bus (i.e. transmit recessive level).
In conventional CAN bus systems, the pull up resistor of the CAN bus has a higher impedance than the dominant driver of any of the CAN nodes, and as a result, the bus transition from the dominant to recessive level (0 to 1) is much slower than a transition from a recessive to a dominant level (1 to 0). Thus, when a sequence comprising 0 1 0 appears on the CAN bus, the duration of the 1 period is significantly shortened because the beginning transition from 0 to 1 is delayed while the end transition from 1 to 0 is not delayed.
Conventional systems have dealt with this problem by shifting the point in time when the receiver samples the value of the currently received bit (also known as the sample point) towards the end of the bit time in order to catch the delayed recessive value. Unfortunately, a delayed sample point provides a smaller time margin for the next bit (which may be dominant and thus not delayed) which in turn narrows the synchronization margin. A narrowed margin interferes with either the high performance of the CAN bus system or the EMC of the system by limiting the CAN baud rate, decreasing oscillator tolerance of the CAN nodes, and/or the need to increase the speed of the CAN driver.
Therefore, there exists a need for a system and a method for operating a bus system that increases the bit rate and improves performance, increases the oscillator tolerance of CAN nodes, and/or enables slowing down the CAN driver/pullup for improved EMC behavior.